View SST25VF064C-80-4I-SCE_7407662.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

?2009 silicon storage technology, inc. s71392-03-000 12/09 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. these specifications are subject to change without notice. data sheet features: ? single voltage read and write operations ?2.7-3.6v ? serial interface architecture ? spi compatible: mode 0 and mode 3 ? dual input/output support ? fast-read dual-output instruction ? fast-read dual i/o instruction ? high speed clock frequency ? 80 mhz for high-speed read (0bh) ? 75 mhz for fast-read dual-output (3bh) ? 50 mhz for fast-read dual i/o (bbh) ? 33 mhz for read instruction (03h) ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption ? active read current: 12 ma (typical @ 80 mhz) for single-bit read) ? active read current: 14 ma (typical @ 75mhz) for dual-bit read) ? standby current: 5 a (typical) ? flexible erase capability ? uniform 4 kbyte sectors ? uniform 32 kbyte overlay blocks ? uniform 64 kbyte overlay blocks ? fast erase ? chip-erase time: 35 ms (typical) ? sector-/block-erase time: 18 ms (typical) ? page-program ? 256 bytes per page ? single and dual input support ? fast page-program time in 1.5 ms (typical) ? end-of-write detection ? software polling the busy bit in status register ? write protection (wp#) ? enables/disables the lock-down function of the status register ? software write protection ? write protection through block-protection bits in sta- tus register ? security id ? one-time programmable (otp) 256 bit, secure id - 64 bit unique, factory pre-programmed identifier - 192 bit user-programmable ? temperature range ? commercial = 0c to +70c ? industrial: -40c to +85c ? packages available ? 16-lead soic (300 mils) ? 8-contact wson (6mm x 8mm) ? 8-lead soic (200 mils) ? all devices are rohs compliant product description the sst 25 series serial flash family features a four-wire, spi-compatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. sst25vf064c spi serial flash memory is manufactured with sst proprietary, high-perfor- mance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reli- ability and manufacturability compared with alternate approaches. the sst25vf064c significantly improves performance and reliability, while lowering power consumption. the device writes (program or erase) with a single power sup- ply of 2.7-3.6v. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash memory technolo- gies. the sst25vf064c device is offered in 16-lead soic (300 mils), 8-contact wson (6mm x 8mm), and 8-lead soic (200 mils) packages. see figure 2 for pin assignments. 64 mbit spi serial dual i/o flash sst25vf064c sst25vf032b32mb serial peripheral interface (spi) flash memory
2 data sheet 64 mbit spi serial dual i/o flash sst25vf064c ?2009 silicon storage technology, inc. s71392-03-000 12/09 figure 1: functional block diagram 1392 b1.0 page buffer, i/o buffers and data latches superflash memory x - decoder control logic address buffers and latches ce# y - decoder sck si/sio 0 so/sio 1 wp# rst#/hold# serial interface
data sheet 64 mbit spi serial dual i/o flash sst25vf064c 3 ?2009 silicon storage technology, inc. s71392-03-000 12/09 pin description figure 2: pin assignments for 16-lead soic, 8-contact wson, and 8-lead soic table 1: pin description symbol pin name functions sck serial clock to provide the timing of the serial interface. commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. si serial data input to transfer commands, addresses, or data serially into the device. inputs are latched on the rising edge of the serial clock. so serial data output to transfer data serially out of the device. data is shifted out on the falling edge of the serial clock. sio[0:1] serial data input/ output for dual i/o mode to transfer commands, addresses, or data serially into the device, or data out of the device. inputs are latched on the rising edge of the serial clock. data is shifted out on the falling edge of the serial clock. these pins are for dual i/o mode. ce# chip enable the device is enabled by a high to low transition on ce#. ce# must remain low for the duration of any command sequence. wp# write protect the write protect (wp#) pin is used to enable/disable bpl bit in the status register. rst#/hold# reset to reset the operation of the device and the internal logic. the device powers on with rst# pin functionality as default. hold to temporarily stop serial communication with spi flash memory while device is selected. this is selected by an instruct ion sequence. see ?reset/hold mode? page 5 for details. v dd power supply to provide power supply voltage: 2.7-3.6v v ss ground t1.0 1392 sck si/sio 0 nc nc nc nc v ss wp# rst#/hold# v dd nc nc nc nc ce# so/sio 1 1392 16-soic p1.0 top view 1392 8-wson p1.0 1 2 3 4 8 7 6 5 ce# so/sio 1 wp# v ss top view v dd rst#/hold# sck si/sio 0 1392 8-soic s3a p1.0 1 2 3 4 8 7 6 5 ce# so wp# v ss v dd rst#/hold# sck si top view
4 data sheet 64 mbit spi serial dual i/o flash sst25vf064c ?2009 silicon storage technology, inc. s71392-03-000 12/09 memory organization the sst25vf064c superflash memory array is orga- nized in uniform 4 kbyte erasable sectors with 32 kbyte overlay blocks and 64 kbyte overlay erasable blocks. device operation the sst25vf064c is accessed through the spi (serial peripheral interface) bus compatible protocol. the spi bus consists of four control lines; chip enable (ce#) is used to select the device, and data is accessed through the serial data input (si), serial data output (so), and serial clock (sck). the sst25vf064c supports both mode 0 (0,0) and mode 3 (1,1) of spi bus operations. the difference between the two modes, as shown in figure 3, is the state of the sck signal when the bus master is in stand-by mode and no data is being transferred. the sck signal is low for mode 0 and sck signal is high for mode 3. for both modes, the serial data in (si) is sampled at the rising edge of the sck clock signal and the serial data output (so) is driven after the falling edge of the sck clock signal. figure 3: spi protocol 1392 f04.0 mode 3 sck si so ce# mode 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode 0 mode 0 high impedance msb msb don't care
data sheet 64 mbit spi serial dual i/o flash sst25vf064c 5 ?2009 silicon storage technology, inc. s71392-03-000 12/09 reset/hold mode the rst#/hold# pin provides either a hardware reset or a hold pin. from power-on, the rst#/hold# pin defaults as a hardware reset pin (rst#). the hold mode for this pin is a user selected option where an ehld instruction enables the hold mode. once selected as a hold pin (hold#), the rst#/hold# pin will be configured as a hold# pin, and goes back to rst# pin only after a power- off and power-on sequence. reset if the rst#/hold# pin is used as a reset pin, rst# pin provides a hardware method for resetting the device. driving the rst# pin high puts the device in normal operating mode. the rst# pin must be driven low for a minimum of t rst time to reset the device. the so pin is in high imped- ance state while the device is in reset. a successful reset will reset the status register to its power-up state (bpl, busy and wel = 0; bp3, bp2, bp1, and bp0 = 1). see table 2 for default power-up modes. a device reset during an active program or erase operation aborts the operation and data of the targeted address range may be corrupted or lost due to the aborted erase or program operation. figure 4: reset timing diagram table 2: reset timing parameters symbol parameter min max units t rst reset pulse width 100 ns t rhz reset to high-z output 105 ns t recr reset recovery from read 100 ns t recp reset recovery from program 10 s t rece reset recovery from erase 1 ms t2.1392 1292 f28.0 ce# so si sck rst# t recr t recp t rece t rst t rhz
6 data sheet 64 mbit spi serial dual i/o flash sst25vf064c ?2009 silicon storage technology, inc. s71392-03-000 12/09 hold operation the ehld instruction enables the hold pin functionality of the rst#/hold# pin. once converted to a hold pin, the rst#/hold# pin functions as a hold pin until the device is powered off and on. after the power cycle, the pin function- ality returns as a reset pin (rst#) after the power on. the hold# pin is used to pause a serial sequence using the spi flash memory, but without resetting the clocking sequence. to activate the hold# mode, ce# must be in active low state. the hold# mode begins when the sck active low state coincides with the falling edge of the hold# signal. the hold mode ends when the hold# signal?s rising edge coincides wi th the sck active low state. if the falling edge of the hold# signal does not coincide with the sck active low state, then the device enters hold mode when the sck next reaches the active low state. similarly, if the rising edge of the hold# signal does not coincide with the sck active low state, then the device exits from hold mode when the sck next reaches the active low state. see figure 5 for hold condition waveform. once the device enters hold mode, so will be in high- impedance state while si and sck can be v il or v ih. if ce# is driven high during a hold condition, the device returns to standby mode. as long as hold# signal is low, the memory remains in the hold condition. to resume communication with the device, hold# must be driven active high, and ce# must be driven active low. see figure 5 for hold timing. figure 5: hold condition waveform write protection sst25vf064c provides software write protection. the write protect pin (wp#) enables or disables the lock-down function of the status regist er. the block-protection bits (bp3, bp2, bp1, bp0, and bpl) in the status register pro- vide write protection to the memory array and the status register. see table 5 for the block-protection description. write protect pin (wp#) the write protect (wp#) pin enables the lock-down func- tion of the bpl bit (bit 7) in the status register. when wp# is driven low, the execution of the write-status-register (wrsr) instruction is determined by the value of the bpl bit (see table 3). when wp# is high, the lock-down func- tion of the bpl bit is disabled. security id sst25vf064c offers a 256-bit se curity id (sec id) fea- ture. the security id space is divided into two parts ? one factory-programmed, 64-bit segment and one user-pro- grammable 192-bit segment. the factory-programmed segment is programmed at sst with a unique number and cannot be changed. the user-programmable segment is left unprogrammed for the customer to program as desired. use the program sid command to program the security id using the address shown in table 7. once programmed, the security id can be locked using the lockout sid com- mand. this prevents any future write to the security id. the factory-programmed portion of the security id can never be programmed, and none of the security id can be erased. active hold active hold active 1392 f05.0 sck hold# table 3: conditions to execute write-status- register (wrsr) instruction wp# bpl execute wrsr instruction l 1 not allowed l0allowed hxallowed t3.0 1392
data sheet 64 mbit spi serial dual i/o flash sst25vf064c 7 ?2009 silicon storage technology, inc. s71392-03-000 12/09 status register the software status register provides status on whether the flash memory array is available for any read or write oper- ation, whether the device is write enabled, and the state of the memory write protection. during an internal erase or program operation, the status register may be read only to determine the completion of an operation in progress. table 4 describes the function of each bit in the software status register. busy the busy bit determines whether there is an internal erase or program operation in progress. a ?1? for the busy bit indi- cates the device is busy with an operation in progress. a ?0? indicates the device is ready for the next valid operation. write enable latch (wel) the write-enable-latch bit indicates the status of the inter- nal memory write enable latch. if the write-enable-latch bit is set to ?1?, it indicates the device is write enabled. if the bit is set to ?0? (reset), it in dicates the device is not write enabled and does not accept any memory write (program/ erase) commands. the write-enable-latch bit is automati- cally reset under the following conditions: ? power-up ? write-disable (wrdi) instruction completion ? write-status register instruction completion ? page-program instruction completion ? dual-input page-program instruction completion ? sector-erase instruction completion ? block-erase instruction completion ? chip-erase instruction completion ? program sid instruction completion ? lockout sid instruction completion table 4: status register bit name function default at power-up read/write 0 busy 1 = internal write operation is in progress 0 = no internal write operation is in progress 0r 1 wel 1 = device is memory write enabled 0 = device is not memory write enabled 0r 2 bp0 indicate current level of block write protection (see table 5) 1 r/w 3 bp1 indicate current level of block write protection (see table 5) 1 r/w 4 bp2 indicate current level of block write protection (see table 5) 1 r/w 5 bp3 indicate current level of block write protection (see table 5) 1 r/w 6 sec 1 1. the security id status will always be ?1? at power-up after a successful execution of the lockout sid instruction; otherwise, the default at power up is ?0?. security id status 1 = security id space locked 0 = security id space not locked 0 1 r 7 bpl 1 = bp3, bp2, bp1, bp0 are read-only bits 0 = bp3, bp2, bp1, bp 0 are readable/writable 0r/w t4.0 1392
8 data sheet 64 mbit spi serial dual i/o flash sst25vf064c ?2009 silicon storage technology, inc. s71392-03-000 12/09 block protection (bp3,bp2, bp1, bp0) the block-protection (bp3, bp2, bp1, bp0) bits define the size of the memory area, as shown in table 5, to be soft- ware protected against any memory write (program or erase) operation. the write-status-register (wrsr) instruction is used to program the bp3, bp2, bp1 and bp0 bits as long as wp# is high or the block-protect-lock (bpl) bit is 0. chip-erase can only be executed if block- protection bits are all 0. after power-up, bp3, bp2, bp1 and bp0 are set to the defaults specified in table 5. block protection lock-down (bpl) wp# pin driven low (v il ), enables the block-protection- lock-down (bpl) bit. when bpl is set to 1, it prevents any further alteration of the bpl, bp3, bp2, bp1, and bp0 bits. when the wp# pin is driven high (v ih ), the bpl bit has no effect and its value is ?don?t care?. after power-up, the bpl bit is reset to 0. security id status (sec) the security id status (sec) bit indicates when the secu- rity id space is locked to prevent a write command. the sec is ?1? after the host issues a lockout sid command. once the host issues a lockout sid command, the sec bit can never be reset to ?0.? table 5: software status register block protection for sst25vf064c protection level status register bit 1 1. default at power-up for bp3, bp2, bp1, and bp0 is ?1111?. (all blocks protected) protected memory address bp3 bp2 bp1 bp0 64 mbit none 0 0 0 0 none upper 1/128 0 0 0 1 7f0000h-7fffffh upper 1/64 0 0 1 0 7e0000h-7fffffh upper 1/32 0 0 1 1 7c0000h-7fffffh upper 1/16 0 1 0 0 780000h-7fffffh upper 1/8 0 1 0 1 700000h-7fffffh upper 1/4 0 1 1 0 600000h-7fffffh upper 1/2 0 1 1 1 400000h-7fffffh all blocks 1 0 0 0 000000h-7fffffh all blocks 1 0 0 1 000000h-7fffffh all blocks 1 0 1 0 000000h-7fffffh all blocks 1 0 1 1 000000h-7fffffh all blocks 1 1 0 0 000000h-7fffffh all blocks 1 1 0 1 000000h-7fffffh all blocks 1 1 1 0 000000h-7fffffh all blocks 1 1 1 1 000000h-7fffffh t5.0 1392
data sheet 64 mbit spi serial dual i/o flash sst25vf064c 9 ?2009 silicon storage technology, inc. s71392-03-000 12/09 instructions instructions are used to read, write (erase and program), and configure the sst25vf064c. the instruction bus cycles are 8 bits each for commands (op code), data, and addresses. the write-enable (wren) instruction must be executed prior any page-program, dual-input page-pro- gram, sector-erase, block-erase, write-status-register, chip-erase, program sid, or lockout sid instructions. the complete list of instructio ns is provided in table 6. all instructions are synchronized off a high to low transition of ce#. inputs will be accept ed on the rising edge of sck starting with the most significant bit. ce# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for read, read-id, and read-status-register instructions). any low to high transition on ce#, before receiving the last bit of an instruction bus cycle, will termi- nate the instruction in progress and return the device to standby mode. instruction commands (op code), addresses, and data are all input from the most significant bit (msb) first. table 6: device operation instructions instruction description op code cycle 1 1. one bus cycle is eight clock periods. address cycle(s) 2 2. address bits above the most significant bit can be either v il or v ih . dummy cycle(s) data cycle(s) read read memory 0000 0011b (03h) 3 0 1 to fast-read dual i/o read memory with dual address input and data output 1011 1011b (bbh) 3 3 3. one bus cycle is four clock periods (dual operation) 1 3 1 to 3 fast-read dual-output read memory with dual output 0011 1011b (3bh) 3 1 1 to 3 high-speed read read memory at higher speed 0000 1011b (0bh) 3 1 1 to sector-erase 4 4. 4kbyte sector erase addresses: use a ms -a 12, remaining addresses are don?t care but must be set either at v il or v ih. erase 4 kbyte of memory array 0010 0000b (20h) 3 0 0 32 kbyte block-erase 5 erase 32kbyte block of memory array 0101 0010b (52h) 3 0 0 64 kbyte block-erase 6 erase 64 kbyte block of memory array 1101 1000b (d8h) 3 0 0 chip-erase erase full memory array 0110 0000b (60h) or 1100 0111b (c7h) 000 page-program to program 1 to 256 data bytes 0000 0010b (02h) 3 0 1 to 256 dual-input page- program to program 1 to 256 data bytes 1010 1001b (a2h) 3 0 1 to 128 3 rdsr 7 read-status-register 0000 0101b (05h) 0 0 1 to ewsr enable-write-status-register 0101 0000b (50h) 0 0 0 wrsr write-status-register 0000 0001b (01h) 0 0 1 wren write-enable 0000 0110b (06h) 0 0 0 wrdi write-disable 0000 0100b (04h) 0 0 0 rdid 8 read-id 1001 0000b (90h) or 1010 1011b (abh) 301 to jedec-id jedec id read 1001 1111b (9fh) 0 0 3 to ehld enable hold# pin functionality of the rst#/ hold# pin 1010 1010b (aah) 0 0 0 read sid read security id 1000 1000b (88h) 1 1 1 to 32 program sid 9 program user security id area 1010 0101b (a5h) 1 0 1 to 24 lockout sid 9 lockout security id programming 1000 0101b (85h) 0 0 0 t6.0 1392
10 data sheet 64 mbit spi serial dual i/o flash sst25vf064c ?2009 silicon storage technology, inc. s71392-03-000 12/09 read (33 mhz) the read instruction, 03h, supports up to 33 mhz read. the device outputs the data starting from the specified address location. the data output stream is continuous through all addresses until terminated by a low to high tran- sition on ce#. the internal address pointer will automati- cally increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will auto matically increment to the beginning (wrap-around) of the address space. for exam- ple, once the data from address location 7fffffh has been read, the next output will be from address location 000000h. the read instruction is initiate d by executing an 8-bit com- mand, 03h, followed by address bits a 23 -a 0 . ce# must remain active low for the duration of the read cycle. see figure 6 for the read sequence. figure 6: read sequence high-speed read (80 mhz) the high-speed read instruction supporting up to 80 mhz read is initiated by executing an 8-bit command, 0bh, fol- lowed by address bits a 23 -a 0 and a dummy byte. ce# must remain active low for the duration of the high-speed read cycle. see figure 7 for the high-speed read sequence. following a dummy cycle, the high-speed read instruction outputs the data starting from the specified address loca- tion. the data output stream is continuous through all addresses until terminated by a low to high transition on ce#. the internal address po inter will automatically incre- ment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automatically incr ement to the beginning (wrap- around) of the address space. for example, once the data from address location 7fffffh is read, the next output is from address location 000000h. 5. 32kbyte block erase addresses: use a ms -a 15, remaining addresses are don?t care but must be set either at v il or v ih. 6. 64kbyte block erase addresses: use a ms -a 16, remaining addresses are don?t care but must be set either at v il or v ih. 7. the read-status-register is continuous with ongoing clock cycles until terminated by a low to high transition on ce#. 8. manufacturer?s id is read with a 0 = 0, and device id is read with a 0 = 1. all other address bits are 00h. the manufacturer?s id and device id output stream is continuous until te rminated by a low-to-high transition on ce#. 9. requires a prior wren command. 1392 f06.0 ce# so si sck add. 012345678 add. add. 03 high impedance 15 16 23 24 31 32 39 40 70 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 d out msb msb msb mode 0 mode 3 d out d out d out d out
data sheet 64 mbit spi serial dual i/o flash sst25vf064c 11 ?2009 silicon storage technology, inc. s71392-03-000 12/09 figure 7: high-speed read sequence fast-read dual-output (75 mhz) the fast-read dual-output (3bh) instruction outputs data up to 75 mhz from the sio 0 and sio 1 pins. to initiate the instruction, execute an 8-bit command (3bh) followed by address bits a23-a0 and a dummy byte on si/sio 0 . fol- lowing a dummy cycle, the fast-read dual-output instruc- tion outputs the data starting from the specified address location on the sio 1 and sio 0 lines. sio 1 outputs, per clock sequence, odd data bits d7, d5, d3, and d1; and sio 0 outputs even data bits d6, d4, d2, and d0. ce# must remain active low for the duration of the fast-read dual- output instruction cycle. see figure 8 for the fast-read dual-output sequence. the data output stream is continuous through all addresses until terminated by a low-to-high transition on ce#. the internal address po inter will automatically incre- ment until the highest memory address is reached. once the highest memory address is reached, the address pointer automatically increments to the beginning (wrap- around) of the address space. for 64 mbit density, once the data from address location 7fffffh has been read the next output will be from address location 000000h. figure 8: fast-read dual output sequence 1392 f07.0 ce# so si sck add. 012345678 add. add. 0b high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 x msb mode 0 mode 3 d out d out d out d out 80 71 72 d out 1392 f08.1 ce# sio 1 sio 0 sck 012345678 28 29 30 31 msb mode 3 mode 0 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 6420642064206420 7531 7531 7531 7531 24-bit address dummy cycle dout msb dout msb dout msb dout 3b n n+1 n+2 n+3 io, switches from input to output x add. add. add. 15 16 high impedance
12 data sheet 64 mbit spi serial dual i/o flash sst25vf064c ?2009 silicon storage technology, inc. s71392-03-000 12/09 fast-read dual i/o (50 mhz) the fast-read dual i/o (bbh) instruction reduces the total number of input clock cycles, which results in faster data access. the device is first selected by driving chip enable ce# low. fast-read dual i/o is initiated by executing an 8- bit command (bbh) on si/sio 0 , thereafter, the device accepts address bits a23-a0 and a dummy byte on si/ sio 0 and so/sio 1 . it offers the capability to input address bits a23-a0 at a rate of two bits per clock. odd address bits a23 through a1 are input on sio 1 and even address bits a22 through a0 are input on sio 0 , alternately for example the most significant bit is input first followed by a23/22, a21/ a20, and so on. each bit is latched at the same rising edge of the serial clock (sck). the input data during the dummy clocks is ?don?t care?. however, the sio 0 and sio 1 pin must be in high-impedance prior to the falling edge of the first data output clock. following a dummy cycle, the fast-read dual i/o instruc- tion outputs the data starting from the specified address location on the sio 1 and sio 0 lines. sio 1 outputs, per clock sequence, odd data bits d7, d5, d3, and d1; and sio 0 outputs even data bits d6, d4, d2, and d0 per clock edge. ce# must remain active low for the duration of the fast-read dual i/o instruction cycle. the data output stream is continuous through all addresses until terminated by a low-to-high transition on ce#. the internal address pointer will automatically increment until the highest memory address is reached. once the highest memory address is reached, the address pointer automatically increments to the beginning (wraparound) of the address space. for example, once the data from address location 7fffffh is read, the next output is from address location 000000h. see figure 9 for the fast-read dual i/o sequence. figure 9: fast-read dual i/o sequence 1392 f29.0 ce# sio 1 sio 0 sck 012345678 91011121314 mode 3 mode 0 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 642064206420 7531 7531 7531 msb 6420642064206420 7531 7531 7531 7531 msb msb msb a23-16 a15-8 a7-0 6 7 39 bb dout dout dout dout n n+1 n+2 n+3 io, switches from input to output x x dummy cycle
data sheet 64 mbit spi serial dual i/o flash sst25vf064c 13 ?2009 silicon storage technology, inc. s71392-03-000 12/09 page-program the page-program instruction programs up to 256 bytes of data in the memory. the selected page address must be in the erased state (ffh) before initiating the page-program operation. a page-program applied to a protected memory area will be ignored. prior to the program operation, the write-enabled (wren) instruction must be executed. ce# must remain active low for the duration of the page-program instruction. the page- program instruction is initiated by executing an 8-bit com- mand, 02h, followed by address bits a23-a0. following the address, at least one byte is needed for the data input. ce# must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t pp for the completion of the internal self-timed page- program operation. see figure 10 for the page-program sequence. for page-program, the memory range for sst25vf064c is set in 256 byte page boundaries. the device handles shifting of more than 256 bytes of data by keeping the last 256 bytes of data shifted as the correct data to be pro- grammed. if the target address for the page-program instruction is not the beginning of the page boundary (a7- a0 are not all zero) and the number of data input exceeds or overlaps the end of the address of the page boundary, the excess data inputs will wrap around and will be pro- grammed at the start of that target page. figure 10: page-program sequence 1392 f30.0 ce# so si sck add. 012345678 add. add. data byte 1 02 high impedance 15 16 23 24 31 32 39 mode 0 mode 3 msb msb msb lsb ce# so si sck 40 41 42 43 44 45 46 47 48 data byte 2 high impedance msb msb msb lsb 50 51 52 53 54 55 2072 49 data byte 3 2073 2074 2075 2076 2077 2078 2079 data byte 256 lsb lsb lsb lsb
14 data sheet 64 mbit spi serial dual i/o flash sst25vf064c ?2009 silicon storage technology, inc. s71392-03-000 12/09 dual-input page-program (50 mhz) dual-input page-program instruction a2h, doubles the data input transfer of normal page-program instruction and supports up to 50mhz. data to be programmed is entered using two i/o pins, sio 1 and sio 0 . prior to the program operation the write-enable (wren) instruction must be executed. the dual-input page-program instruction is entered by driving ce# low, followed by the instruction code, a2h, three address bytes, and at least one data byte on serial data inputs sio 1 and sio 0 pins. ce# must be driven low for the entire duration of the sequence. the dual-input page-program instruction programs up to 256 bytes of data in the memory. the selected page address must be in the erased state (ffh) before initiating the page-program operation. a dual-input page-program applied to a protected me mory area will be ignored. ce# must be driven high after the seventh and eight bit of the last data byte has been latched; otherwise, the dual input program instruction is not executed. once ce# is driven high the instruction is executed and the user may poll the wel and busy bit of the software status register or wait tpp for the completion of the internal self-timed page- program operation. see figure 10 for the dual-input-page- program sequence. for dual-input page-program, the memory range for the sst25vf064c is set in 256 byte page boundaries. the device handles shifting of more than 256 bytes of data by keeping the last 256 bytes of data shifted as the correct data to be programmed. if the target address for the page- program instruction is not the beginning of the page bound- ary (a7-a0 are not all zero) and the number of data input exceeds or overlaps the end of the address of the page boundary, the excess data in puts will wrap around and will be programmed at the start of that target page. figure 11: dual-input page-program 1392 f31.0 ce# sio 1 sio 0 sck 012345678 910 mode 3 mode 0 28 29 30 31 32 33 34 35 36 37 28 39 40 41 42 43 44 45 46 64206420 7531 7531 msb 64206420 7531 7531 msb msb 47 6420 7531 3210 23 22 21 24-bit address (1) msb msb data byte 1 data byte 2 data byte 3 data byte 4 data byte 256 high impedance a2 1052 1053 1054 1055
data sheet 64 mbit spi serial dual i/o flash sst25vf064c 15 ?2009 silicon storage technology, inc. s71392-03-000 12/09 sector-erase the sector-erase instruction clears all bits in the selected 4 kbyte sector to ffh. a sector-erase instruction applied to a protected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of any command sequence. the sector-erase instruction is initiated by executing an 8-bit command, 20h, followed by address bits a 23 -a 0 . address bits a ms -a 12 (a ms = most significant address) are used to determine the sector address (sa x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruction is executed. poll the busy bit in the software status register or wait t se for the completion of the internal self-timed sector-erase cycle. see figure 12 for the sector-erase sequence. figure 12: sector-erase sequence ce# so si sck add. 012345678 add. add. 20 high impedance 15 16 23 24 31 mode 0 mode 3 1392 f13.0 msb msb
16 data sheet 64 mbit spi serial dual i/o flash sst25vf064c ?2009 silicon storage technology, inc. s71392-03-000 12/09 32-kbyte and 64-kbyte block-erase the 32-kbyte block-erase instruction clears all bits in the selected 32 kbyte block to ffh. a block-erase instruction applied to a protected memo ry area will be ignored. the 64-kbyte block-erase instruction clears all bits in the selected 64 kbyte block to ffh. a block-erase instruction applied to a protected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of any command sequence. the 32-kbyte block- erase instruction is initiated by executing an 8-bit com- mand, 52h, followed by address bits a 23 -a 0 . address bits a ms -a 15 (a ms = most significant address) are used to determine block address (ba x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruction is executed. the 64-kbyte block-erase instruction is initi- ated by executing an 8-bit command d8h, followed by address bits a 23 -a 0 . address bits a ms -a 15 are used to determine block address (ba x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruction is executed. poll the busy bit in the software status register or wait t be for the completion of the internal self-timed 32- kbyte block-erase or 64-kbyte block-erase cycles. see figure 13 for the 32-kbyte block-erase sequence and fig- ure 14 for the 64-kbyte block-erase sequence. figure 13: 32-kbyte block-erase sequence figure 14: 64-kbyte block-erase sequence ce# so si sck addr 012345678 addr addr 52 high impedance 15 16 23 24 31 mode 0 mode 3 1392 f32.0 msb msb ce# so si sck addr 012345678 addr addr d8 high impedance 15 16 23 24 31 mode 0 mode 3 1327 f33.0 msb msb
data sheet 64 mbit spi serial dual i/o flash sst25vf064c 17 ?2009 silicon storage technology, inc. s71392-03-000 12/09 chip-erase the chip-erase instruction clear s all bits in the device to ffh. a chip-erase instruction will be ignored if any of the memory area is protected. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of the chip-erase instruction sequence. initiate the chip-erase instruction by executing an 8-bit command, 60h or c7h. ce# must be driven high before the instruction is executed. poll the busy bit in the software status register or wait t ce for the comple- tion of the internal self-timed chip-erase cycle. see figure 15 for the chip-erase sequence. figure 15: chip-erase sequence read security id to execute a read sid operation, the host drives ce# low, sends the read sid command cycle (88h), one address cycle, and then one dummy cycl e. each cycle is eight bits long, most significant bit first. after the dummy cycle, the device outputs data on the fall- ing edge of the sck signal, starting from the specified address location. the data output stream is continuous through all sid addresses until terminated by a low-to-high transition on ce#. the internal address pointer automati- cally increments until the last sid address is reached, then outputs wrap around until ce# goes high. lockout security id the lockout sid instruction prevents any future changes to the security id. prior to the lockout sid operation, the write-enable (wren) instruction must be executed. to execute a lockout sid, the host drives ce# low, sends the lockout sid command cycle (85h), then drives ce# high. a cycle is 8 bits long, most signi ficant bit first. the user may poll the busy bit in the software status register or waits t psid for the completion of the lockout sid operation. program security id the program sid instruction programs one to 24 bytes of data in the user-programmable, security id space. the device ignores a program sid instruction pointing to an invalid or protected address, see table 7. prior to the pro- gram operation, execute wren. to execute a program sid operation, the host drives ce# low, sends the program sid command cycle (a5h), one address cycle, the data to be programmed, then drives ce# high. the programmed data must be between 1 to 24 bytes and in whole byte increments. to determine the completion of the internal, self-timed program sid opera- tion, poll the busy bit in the software status register, or wait t psid for the completion of the internal self-timed program sid operation. ce# so si sck 01234567 60 or c7 high impedance mode 0 mode 3 1392 f16.0 msb table 7: program security id program security id address range pre-programmed at factory 00h ? 07h user programmable 08h ? 1fh t7.0 1392
18 data sheet 64 mbit spi serial dual i/o flash sst25vf064c ?2009 silicon storage technology, inc. s71392-03-000 12/09 read-status-register (rdsr) the read-status-register (rdsr) instruction allows read- ing of the status register. the status register may be read at any time even during a write (program/erase) operation. when a write operation is in progress, the busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. ce# must be driven low before the rdsr instruction is entered and remain low until the status data is read. read- status-register is continu ous with ongoing clock cycles until it is terminated by a low to high transition of the ce#. see figure 16 for the rdsr instruction sequence. figure 16: read-status-register (rdsr) sequence write-enable (wren) the write-enable (wren) instruction sets the write- enable-latch bit in the status register to ?1? allowing write operations to occur. the wren instruction must be exe- cuted prior to any write (program/erase) operation. the wren instruction may also be used to allow execution of the write-status-register (wrsr) instruction; however, the write-enable-latch bit in the status register will be cleared upon the rising edge ce# of the wrsr instruction. ce# must be driven high before the wren instruction is executed. figure 17: write enable (wren) sequence 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1392 f17.0 mode 3 sck si so ce# bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05 mode 0 high impedance status register out msb msb ce# so si sck 01234567 06 high impedance mode 0 mode 3 1392 f18.0 msb
data sheet 64 mbit spi serial dual i/o flash sst25vf064c 19 ?2009 silicon storage technology, inc. s71392-03-000 12/09 write-disable (wrdi) the write-disable (wrdi) instruction resets the write- enable-latch bit to ?0,? thereby, preventing any new write operations. the wrdi instruction will not terminate any program or erase operation in progress. any program or erase operation in progress will continue after executing the wrdi instruction. ce# must be driven high before the wrdi instruction is executed. figure 18: write disable (wrdi) sequence ce# so si sck 01234567 04 high impedance mode 0 mode 3 1392 f19.0 msb
20 data sheet 64 mbit spi serial dual i/o flash sst25vf064c ?2009 silicon storage technology, inc. s71392-03-000 12/09 enable-write-stat us-register (ewsr) the enable-write-status-register (ewsr) instruction arms the write-status-register (wrsr) instruction and opens the status register for alteration. the write-status- register instruction must be executed immediately after the execution of the enable-write-status-register instruction. this two-step instruction sequence of the ewsr instruc- tion followed by the wrsr instruction works like software data protection (sdp) command structure which prevents any accidental alteration of the status register values. ce# must be driven low before the ewsr instruction is entered and must be driven high before the ewsr instruction is executed. write-status-register (wrsr) the write-status-register instruction writes new values to the bp3, bp2, bp1, bp0, and bpl bits of the status regis- ter. ce# must be driven low before the command sequence of the wrsr instruction is entered and driven high before the wrsr instruction is executed. see figure 19 for ewsr or wren and wrsr instruction sequences. executing the write-status-register instruction will be ignored when wp# is low and bpl bit is set to ?1?. when the wp# is low, the bpl bit can only be set from ?0? to ?1? to lock-down the status register, but cannot be reset from ?1? to ?0?. when wp# is high, the lock-down function of the bpl bit is disabled and the bpl, bp0, bp1, bp2, and bp3 bits in the status register can all be changed. as long as bpl bit is set to ?0? or wp# pin is driven high (v ih ) prior to the low- to-high transition of the ce# pin at the end of the wrsr instruction, the bits in the status register can all be altered by the wrsr instruction. in this case, a single wrsr instruction can set the bpl bit to ?1? to lock down the status register as well as altering the bp0, bp1, bp2, and bp3 bits at the same time. see table 3 for a summary descrip- tion of wp# and bpl functions. figure 19: enable-write-status-register (ewsr) or write-enable (wren) and write-status-register (wrsr) sequence 1392 f20.0 mode 3 high impedance mode 0 status register in 76543210 msb msb msb 01 mode 3 sck si so ce# mode 0 50 or 06 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
data sheet 64 mbit spi serial dual i/o flash sst25vf064c 21 ?2009 silicon storage technology, inc. s71392-03-000 12/09 enable-hold (ehld) the 8-bit command, aah, enable-hold instruction enables the hold functionality of the rst#/hold# pin. ce# must remain active low for the duration of the enable-hold instruction sequence. ce# must be driven high before the instruction is executed. see figure 20 for the enable-hold instruction sequence. figure 20: enable-hold sequence read-id (rdid) the read-id instruction (rdid) identifies the device as sst25vf064c and manufacturer as sst. the device information can be read from executing an 8-bit command, 90h or abh, followed by address bits a 23 -a 0 . following the read-id instruction, the manufacturer?s id is located in address 00000h and the device id is located in address 00001h. once the device is in read-id mode, the manu- facturer?s and device id output data toggles between address 00000h and 00001h until terminated by a low to high transition on ce#. after ce# is driven high, the device is put into standby mode. refer to tables 8 and 9 for device identification data. figure 21: read-id sequence ce# so si sck 01234567 aa high impedance mode 0 mode 3 1203 f21.0 msb 1392 f21.0 ce# so si sck 00 012345678 00 add 1 90 or ab high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 bf device id bf device id note: the manufacturer's and device id output stream is continuous until terminated by a low to high transition on ce#. 1. 00h will output the manfacturer's id first and 01h will output device id first before toggling between the two. high impedance mode 3 mode 0 msb msb msb table 8: product identification address data manufacturer?s id 00000h bfh device id sst25vf064c 00001h 4bh t8.0 1392
22 data sheet 64 mbit spi serial dual i/o flash sst25vf064c ?2009 silicon storage technology, inc. s71392-03-000 12/09 jedec read-id the jedec read-id instruction identifies the device as sst25vf064c and the manufacturer as sst. the device information can be read from executing the 8-bit command, 9fh. following the jedec read-id instruction, the 8-bit manufacturer?s id, bfh, is output from the device. after that, a 24-bit device id is shifted out on the so pin. byte 1, bfh, identifies the manufacturer as sst. byte 2, 25h, iden- tifies the memory type as spi serial flash. byte 3, 4bh, identifies the device as sst25vf064c. the instruction sequence is shown in figure 22. the jedec read id instruction is terminated by a low to high transition on ce# at any time during data output. figure 22: jedec read-id sequence 25 4b 1392 f22.0 ce# so si sck 012345678 high impedance 15 16 14 28 29 30 31 bf mode 3 mode 0 msb msb 9 10111213 1718 9f 19 20 21 22 23 24 25 26 27 table 9: jedec read-id data manufacturer?s id device id memory type memory capacity byte1 byte 2 byte 3 bfh 25h 4bh t9.0 1392
data sheet 64 mbit spi serial dual i/o flash sst25vf064c 23 ?2009 silicon storage technology, inc. s71392-03-000 12/09 electrical specifications absolute maximum stress ratings applied conditions greater than thos e listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. expo sure to absolute maximum stress rating conditions may affect device reliability. temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. output shorted for no more than one second. no more than one output shorted at a time. operating range range ambient temp v dd commercial industrial 0c to +70c -40c to +85c 2.7-3.6v 2.7-3.6v ac conditions of test input rise/fall time . . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figure 28 table 10: dc operating characteristics (vdd = 2.7-3.6v) symbol parameter limits test conditions min max units i ddr read current 12 ma ce# = 0.1 v dd /0.9 v dd @33 mhz, so = open i ddr2 high-speed read current 25 ma ce# = 0.1 v dd /0.9 v dd @80 mhz, so = open i ddr3 fast-read dual-output/dual i/o current 25 ma ce# = 0.1 v dd /0.9 v dd @75/50 mhz i ddw program and erase current 25 ma ce# = v dd i sb1 standby current 20 a ce# = v dd , v in = v dd or v ss i li input leakage current 1 a v in = gnd to v dd , v dd = v dd max i lo output leakage current 1 a v out = gnd to v dd , v dd = v dd max v il input low voltage 0.8 v v dd = v dd min v ih input high voltage 0.7 v dd vv dd = v dd max v ol output low voltage 0.2 v i ol = 100 a, v dd = v dd min v oh output high voltage v dd -0.2 v i oh = -100 a, v dd = v dd min t10.0 1392 table 11: capacitance (t a = 25c, f = 1 mhz, other pins open) parameter description test condition maximum c out 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. output pin capacitance v out = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t11.0 1392
24 data sheet 64 mbit spi serial dual i/o flash sst25vf064c ?2009 silicon storage technology, inc. s71392-03-000 12/09 table 12: reliability characteristics symbol parameter minimum spec ification units test method n end 1 endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t12.0 1392 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. table 13: ac operating characteristics symbol parameter 33 mhz 50 mhz 75/80 mhz units min max min max min max f clk 1 1. maximum clock frequency for read instruction, 03h, is 33 mhz maximum clock frequency fast-read dual-output (3bh) is 75 mhz maximum clock frequency fast-read dual i/o (bbh) is 50 mhz maximum clock frequency for high-speed read, obh, is 80 mhz maximum clock frequency for dual-input page-program, a2h, is 50 mhz serial clock frequency high-speed read 33 50 75/80 mhz t sckh serial clock high time 13 9 6 ns t sckl serial clock low time 13 9 6 ns t sckr 2 2. maximum rise and fall time may be limited by t sckh and t sckl requirements serial clock rise time (slew rate) 0.1 0.1 0.1 v/ns t sckf serial clock fall time (slew rate) 0.1 0.1 0.1 v/ns t ces 3 3. relative to sck. ce# active setup time 5 5 5 ns t ceh 3 ce# active hold time 5 5 5 ns t chs 3 ce# not active setup time 5 5 5 ns t chh 3 ce# not active hold time 5 5 5 ns t cph ce# high time 50 50 50 ns t chz 4 4. not 100% tested in production. ce# high to high-z output 7 7 7 ns t clz sck low to low-z output 0 0 0 ns t ds data in setup time 3 3 2 ns t dh data in hold time 5 5 4 ns t hls hold# low setup time 5 5 5 ns t hhs hold# high setup time 5 5 5 ns t hlh hold# low hold time 5 5 5 ns t hhh hold# high hold time 5 5 5 ns t hz 4 hold# low to high-z output 7 7 7 ns t lz 4 hold# high to low-z output 7 7 7 ns t oh output hold from sck change 0 0 0 ns t v output valid from sck 15 10 6 ns t se sector-erase 25 25 25 ms t be block-erase 25 25 25 ms t sce chip-erase 50 50 50 ms t pp page-program 2.5 2.5 2.5 ms t psid program security id 1.0 1.0 1.0 ms t13.1 1392
data sheet 64 mbit spi serial dual i/o flash sst25vf064c 25 ?2009 silicon storage technology, inc. s71392-03-000 12/09 figure 23: serial input timing diagram figure 24: serial output timing diagram figure 25: hold timing diagram high-z high-z ce# so si sck msb lsb t ds t dh t chh t ces t ceh t chs t sckr t sckf t cph 1392 f23.0 1392 f24.0 ce# si so sck msb t clz t v t sckh t chz t oh t sckl lsb t hz t lz t hhh t hls t hhs 1392 f25.0 hold# ce# sck so si t hlh
26 data sheet 64 mbit spi serial dual i/o flash sst25vf064c ?2009 silicon storage technology, inc. s71392-03-000 12/09 power-up specifications all functionalities and dc specif ications are specified for a v dd ramp rate of greater than 1v per 100 ms (0v to 3v in less than 300 ms). if the vdd ramp rate is slower than 1v/100 ms, a hardware reset is required. the recom- mended v dd power-up to reset# high time shou ld be greater than 100 s to ensure a proper reset. see table 14 and figures 26 and 27 for more information. figure 26: power-up reset diagram figure 27: power-up timing diagram table 14: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. v dd min to read operation 100 s t pu-write 1 v dd min to write operation 100 s t14.0 1392 1203 f37.0 v dd reset# ce# t pu-read v dd min 0v v ih t recr note: see table 2 on page 5 for t recr parameter. time v dd min v dd max v dd device fully accessible t pu-read t pu-write chip selection is not allowed. all commands are rejected by the device. 1392 f26.0
data sheet 64 mbit spi serial dual i/o flash sst25vf064c 27 ?2009 silicon storage technology, inc. s71392-03-000 12/09 figure 28: ac input/output reference waveforms 1392 f37.0 reference points output input v ht v lt v ht v lt v iht v ilt ac test inputs are driven at v iht (0.9v dd ) for a logic ?1? and v ilt (0.1v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v ht (0.6v dd ) and v lt (0.4v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v ht - v high te s t v lt - v low te s t v iht - v input high test v ilt - v input low test
28 data sheet 64 mbit spi serial dual i/o flash sst25vf064c ?2009 silicon storage technology, inc. s71392-03-000 12/09 product ordering information valid combinations for sst25vf064c SST25VF064C-80-4I-SCE sst25vf064c-80-4i-q2ae sst25vf064c-80-4c-q2ae sst25vf064c-80-4i-s3ae note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. sst 25 vf 064 c - 80 - 4i - sc e xx x xxxx x -xx -xx -xx x environmental attribute e 1 = non-pb package modifier c = 16 leads a = 8 contacts package type s = soic (300 mil body width) q2 = wson (6mm x 8mm) s3 = soic (200 mil body width) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles operating frequency 80 = 80 mhz version c = page-program device density 064 = 64 mbit voltage v = 2.7-3.6v product series 25 = serial peripheral interface flash memory 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?.
data sheet 64 mbit spi serial dual i/o flash sst25vf064c 29 ?2009 silicon storage technology, inc. s71392-03-000 12/09 packaging diagrams figure 29: 16-lead plastic small outline integrated circuit (soic) sst package code sc 16.soic-sc-ill.3 n ote: 1. complies w ith jedec p ub lication 95 ms-013 aa dimensions (except as noted), altho u gh some dimensions may b e more stringent. ? = jedec min is 10.10; sst min (10.0 8 ) is less stringent ? = jedec min is 0.40; sst min (0.3 8 ) is less stringent 2. all linear dimensions are in metric (min/max). 3. coplanarity: 0.1 (.05) mm. 4. maxim u m allo w a b le mold flash is 0.15mm at the package ends, and 0.25mm b et w een leads. .33 .51 10.0 8 ? 10.50 1.27 bsc .10 .30 2.35 2.65 .23 .32 .3 8 ? 1.27 .020x45 7 4 places 7 4 places 10.00 10.65 7.40 7.60 pin #1 identifier
30 data sheet 64 mbit spi serial dual i/o flash sst25vf064c ?2009 silicon storage technology, inc. s71392-03-000 12/09 figure 30: 8-contact very-very-thin small outline no-lead (wson) sst package code: q2a n ote: 1. all linear dimensions are in millimeters (max/min). 2. untoleranced dimensions are nominal target dimensions. 3. the external paddle is electrically connected to die b ack-side and v ss . this paddle can b e soldered to the pc b oard; sst s u ggests connecting this paddle to v ss of the u nit. connection of this paddle to any other v oltage potential will res u lt in shorts and/or electrical malf u nction of the de v ice. 8 - w son-6x 8 -q2a-2.0 4. 8 1.27 bsc pin #1 0.45 0.35 6.0 6.00 0.10 8 .00 0.10 0.55 0.45 pin #1 top v ie w bottom v ie w cross sectio n side v ie w 1mm 0.076 detail a-a a a 0. 8 0 0.70 0.2 0.05 max 0. 8 0 0.70
data sheet 64 mbit spi serial dual i/o flash sst25vf064c 31 ?2009 silicon storage technology, inc. s71392-03-000 12/09 figure 31: 8-lead small outlin e integrated circuit (soic) sst package code s3a table 15: revision history number description date 00 ? initial release of data sheet sep 2008 01 ? added 8-contact wson q2a package ? added security id information throughout ? updated table 6 on page 9 ? revised ?fast-read dual-output (75 mhz)? on page 11 and ?fast-read dual i/o (50 mhz)? on page 12. ? modified figure 8 on page 11. ? updated table 13 on page 24 ? added commercial temperature range in features, page 1; operating range, page 23; and product ordering information, page 28 apr 2009 02 ? added 8-lead soic s3a package sep 2009 03 ? changed max value of i ddr2 and i ddw to 25ma in table 10 on page 23 dec 2009 8-soic-5x8-s3a-1.0 note: 1. all linear dimensions are in millimeters (max/min). 2. coplanarity: 0.1 mm 3. maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads. top view side view end view 7.34 7.08 8.10 7.70 5.38 5.18 pin #1 identifier 0.48 0.35 0.25 0.19 0.80 0.50 10 4 places 1mm 0 8 1.27 bsc 0.25 0.05 2.16 1.75 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

▲Up To Search▲

Price & Availability of SST25VF064C-80-4I-SCE

	To Download SST25VF064C-80-4I-SCE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .